Integrated circuits (ICs) are commonly made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or FET features are reduced to reduce corresponding device minimum dimensions including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions (e.g., channel layer depth), gate dielectric thickness and junction depths. Reducing the device size increases the device density and performance, and reduces device-operating conditions, i.e., chip (and thus device) supply voltages and voltage swings. Consequently, as a result of scaling, otherwise seemingly negligible device-to-device variations (e.g., length, width and threshold) have caused serious design problems, especially in signal critical circuits such as memory sense amplifiers.
A typical CMOS circuit includes paired complementary devices, i.e., an N-type FET (NFET) paired with a corresponding P-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite one another, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET in this example) is off, and not conducting (ideally modeled as an open switch) and, vice versa. So, for example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (often referred to as Vdd) and ground (GND).
An ideal static random access memory (SRAM) cell includes a balanced pair of cross-coupled inverters storing a single data bit with a high at the output of one inverter and a low at the output of the other inverter. A pair of pass gates (also ideally, a balanced pair of FETs) selectively connects the complementary outputs of the cross-coupled inverter to a corresponding complementary pair of bit lines. A word line connected to the gates of the pass gate FETs selects the cell, connecting the cell contents to the corresponding complementary pair of bit lines. An N-by-M SRAM array is organized as N rows of word lines by M columns of line pairs. Accessing a K bit single word (for a read or a write) from the array entails driving one of the N word lines. During a read operation, each cell on the selected word line couples its contents to its corresponding bit line pair through NFET pass gates. Each cell on a selected column line may be coupled to a simple sense amplifier (often referred to as a sense amp and ideally embodied as a matched pair of cross-coupled common-source devices connected between a bit line pair and an enable source line). Since the bit line pair is typically pre-charged to some common voltage, initially, the internal (to the cell) low voltage rises until one of the bit line pairs drops sufficiently to develop a small difference signal (e.g., 30 mV) on the bit line pair.
Since a design shape printed and formed at different locations always has some variation in the way it prints, imbalances in a matched cell device pair or a matched sense amp pair is inevitable. These imbalances unbalance the pair and may seriously erode the sense signal margin and even cause data sense errors. This erosion may be even worse in partially depleted (PD) silicon on insulator (SOI) CMOS SRAM cells and circuits, because PD SOI devices are subject to floating body effects. Floating body effects, also referred to as body effects or history effects, occur in completely or partially isolated (e.g., where body resistance may have rendered body contacts ineffective) devices, where the device substrate or body is floating or essentially floating. As a floating body device switches off, charge (i.e., from majority carriers) remains in the device body beneath the channel. Device leakage and parasitic bipolar effects may add to the charge. Charge builds at isolated devices as the chip operates because the charge from fast switching devices is injected into locally isolated body pockets faster than it dissipates. Eventually, the injected charge reaches some steady state value that acts as a substrate bias, e.g., shifting the threshold voltage (VT) for the device. This steady state change depends upon the switching history of each particular device and is thus also referred to as the history effects for the particular device.
The result of the body effects may be that two identical-by-design adjacent devices exhibit some difference that may be time varying, e.g., from changing circuit conditions during read and write operations. Body effects can unbalance a matched pair of devices in a sense amp, for example. Sense amp mismatches can thus cause the data to be read erroneously. U.S. patent application Ser. No. 11/055,416, entitled “SRAM and Dual Single Ended Bit Sense for an SRAM,” discloses a domino sensing technique for this problem by replacing the sense amps with domino sensing. Generally, data from a given cell is amplified through an inverter and gated with a read signal. While this technique may reduce erroneous read operations, it may pose a problem during a write operation. If the write signal arrives later than the word signal, then the cell can erroneously start reading the data (referred to as a “false read”), causing a glitch at the output and corrupting the output boundary latches.
A need therefore exists for improved methods and apparatus for SRAM data sense reliability with suppression of such false reads.